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the mpc7410 is a powerpc? microprocessor. the mpc7410 is a reduced instruction set computing (risc) microprocessor that implements the powerpc instruction set architecture. this document describes pertinent electrical and physical characteristics of the mpc7410. for functional characteristics of the processor, refer to the mpc7410 risc microprocessor user?s manual . this document contains the following topics: to p i c p a ge section 1.1, ?overview? 2 section 1.2, ?features? 2 section 1.3, ?general parameters? 7 section 1.4, ?electrical and thermal characteristics? 8 section 1.5, ?pin assignments? 24 section 1.6, ?pinout listings? 25 section 1.7, ?package description? 29 section 1.8, ?system design information? 31 section 1.9, ?document revision history? 45 section 1.10, ?ordering information? 48 to locate any published errata or updates for this document, refer to the web site at http://www.motorola.com/semiconductors. advance information mpc7410ec rev. 3, 4/2004 mpc7410 risc microprocessor hardware specifications
2 mpc7410 risc microprocessor hardware specifications motorola overview overview 1.1 overview the mpc7410 is the second implementation of the fourth generation (g4) microprocessors from motorola. the mpc7410 implements the full powerpc 32-bit architecture and is targeted at both computing and embedded systems applications. some comments on the mpc7410 with respect to the mpc750: the mpc7410 adds an implementation of the new altivec? technology instruction set. the mpc7410 includes significant improvements in memory subsystem (mss) bandwidth and offers an optional, high-bandwidth mpx bus interface. the mpc7410 adds full hardware-based multiprocessing capability, including a five-state cache coherency protocol (four mesi states plus a fifth state for shared intervention). the mpc7410 is implemented in a next generation process technology for core frequency improvement. the mpc7410 floating-point unit has been improved to make latency equal for double- and single-precision operations involving multiplication. the completion queue has been extended to eight slots. there are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the branch unit. the mpc750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute, complete/writeback). some comments on the mpc7410 with respect to the mpc7400: the mpc7410 adds configurable direct-mapped sram capability to the l2 cache interface. the mpc7410 adds 32-bit interface support to the l2 cache interface. the mpc7410 implements a 19th l2 address pin (l2aspare on the mpc7400) in order to support additional address range. the mpc7410 removes support for 3.3-v i/o on the l2 cache interface. figure 1 shows a block diagram of the mpc7410. 1.2 features this section summarizes features of the mpc7410 implementation of the powerpc architecture. major features of the mpc7410 are as follows: branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving two speculations) ? up to one speculative stream in execution, one additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, four-way set-associative branch target instruction cache (btic) for eliminating branch delay slots dispatch unit ? full hardware detection of dependencies (resolved in the execution units) ? dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, altivec permute, altivec alu) ? serialization control (predispatch, postdispatch, execution serialization)
motorola mpc7410 risc microprocessor hardware specifications 3 features figure 1. mpc7410 block diagram srs (original) additional features ?time base counter/decrementer clock multiplier jtag/cop interface thermal/power management performance monitor + + fetcher branch processing btic (64-entry) + x fpscr vscr fpscr l2cr ctr lr pa ea + x instruction unit unit instruction queue (6-word) 2 instructions reservation integer system dispatch unit 64-bit (2 instructions) 128-bit (4 instructions) 32-bit floating- point unit 32-bit 64-bit reservation load/store unit (ea calculation) finished 32-bit completion unit completion queue (8-entry) tags 32-kbyte d cache memory subsystem instruction data reload l2 controller bus interface unit l2 castout 32-bit address bus 64-bit data bus 19-bit l2 address bus 64- or 32-bit l2 data bus integer station reservation station reservation station register unit unit 1 unit 2 reservation station fpr file 6 rename buffers station (2-entry) gpr file 6 rename buffers vciu vector vector alu reservation station reservation station permute vr file 6 rename buffers unit 64-bit reload table vsiu vfpu 128-bit 128-bit ability to complete up completed instruction mmu srs (shadow) 128-entry ibat array itlb bht (512-entry) l2 miss data transaction table tags 32-kbyte i cache data reload buffer instruction reload buffer to two instructions per clock data mmu 128-entry dbat array dtlb load fold l1 stores stores operations l2 data transaction vector touch queue l2pmcr queue queue queue l2 tags
4 mpc7410 risc microprocessor hardware specifications motorola features features decode ? register file access ? forwarding control ? partial instruction decode completion ? eight-entry completion buffer ? instruction tracking and peak completion of two instructions per cycle ? completion of instructions in program order while supporting out-of-order instruction execution, completion serialization, and all instruction flow changes fixed point units (fxus) that share 32 gprs for integer operands ? fixed point unit 1 (fxu1)?multiply, divide, shift, rotate, arithmetic, logical ? fixed point unit 2 (fxu2)?shift, rotate, arithmetic, logical ? single-cycle arithmetic, shifts, rotates, logical ? multiply and divide support (multi-cycle) ? early out multiply three-stage floating-point unit and a 32-entry fpr file ? support for ieee-754 standard single- and double-precision floating-point arithmetic ? three-cycle latency, one-cycle throughput (single- or double-precision) ? hardware support for divide ? hardware support for denormalized numbers ? time deterministic non-ieee mode system unit ? executes cr logical instructions and miscellaneous system instructions ? special register transfer instructions altivec unit ? full 128-bit data paths ? two dispatchable units: vector permute unit and vector alu unit. ? contains its own 32-entry 128-bit vector register file (vrf) with 6 renames ? the vector alu unit is further subdivided into the vector simple integer unit (vsiu), the vector complex integer unit (vciu), and the vector floating-point unit (vfpu). ? fully pipelined load/store unit ? one-cycle load or store cache access (byte, half word, word, double word) ? two-cycle load latency with 1-cycle throughput ? effective address generation ? hits under misses (multiple outstanding misses) ? single-cycle unaligned access within double-word boundary ? alignment, zero padding, sign extend for integer register file ? floating-point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering
motorola mpc7410 risc microprocessor hardware specifications 5 features ? executes the cache and tlb instructions ? big- and little-endian byte addressing supported ? misaligned little-endian supported ? supports fxu, fpu, and altivec load/store traffic ? complete support for all four architecture altivec dst streams level 1 (l1) cache structure ? 32k, 32-byte line, eight-way set-associative instruction cache (il1) ? 32k, 32-byte line, eight-way set-associative data cache (dl1) ? single-cycle cache access ? pseudo least-recently-used (lru) replacement ? data cache supports altivec lru and transient instructions algorithm ? copy-back or write-through data cache (on a page-per-page basis) ? supports all powerpc memory coherency modes ? nonblocking instruction and data cache ? separate copy of data cache tags for efficient snooping ? no snooping of instruction cache except for icbi instruction level 2 (l2) cache interface ? internal l2 cache controller and tags; external data srams ? 512k, 1m, and 2-mbyte two-way set-associative l2 cache support ? copy-back or write-through data cache (on a page basis, or for all l2) ? 32-byte (512-k), 64-byte (1-m), or 128-byte (2-m) sectored line size ? supports pipelined (register-register) synchronous burstrams and pipelined (register-register) late write synchronous burstrams ? supports direct-mapped mode for 256k, 512k, 1m, or 2-mbyte of sram (either all, half, or none of l2 sram must be configured as direct-mapped) ? core-to-l2 frequency divisors of 1, 1.5, 2, 2.5, 3, 3.5, and 4 supported ? 64-bit data bus which also supports 32-bit bus mode ? selectable interface voltages of 1.8 and 2.5 v memory management unit ? 128-entry, two-way set-associative instruction tlb ? 128-entry, two-way set-associative data tlb ? hardware reload for tlbs ? four instruction bats and four data bats ? virtual memory support for up to 4 exabytes (2 52 ) of virtual memory ? real memory support for up to 4 gigabytes (2 32 ) of physical memory ? snooped and invalidated for tlbi instructions efficient data flow ? all data buses between vrf, load/store unit, dl1, il1, l2, and the bus are 128 bits wide ? dl1 is fully pipelined to provide 128 bits/cycle to/from the vrf ? l2 is fully pipelined to provide 128 bits per l2 clock cycle to the l1s ? up to eight outstanding, out-of-order, cache misses between dl1 and l2/bus
6 mpc7410 risc microprocessor hardware specifications motorola features features ? up to seven outstanding, out-of-order transactions on the bus ? load folding to fold new dl1 misses into older, outstanding load and store misses to the same line ? store miss merging for multiple store misses to the same line. only coherency action taken (that is, address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). ? two-entry finished store queue and four-entry completed store queue between load/store unit and dl1 ? separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dl1 and l2 bus interface ? mpx bus extension to 60x processor interface ? mode-compatible with 60x processor interface ? 32-bit address bus ? 64-bit data bus ? bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported ? selectable interface voltages of 1.8, 2.5, and 3.3 v power management ? low-power design with thermal requirements very similar to mpc740 and mpc750 ? low-voltage processor core ? selectable interface voltages can reduce power in output buffers ? three static power saving modes: doze, nap, and sleep ? dynamic power management testability ? lssd scan design ? ieee 1149.1 jtag interface ? array built-in self test (abist)?factory test only ? redundancy on l1 data arrays and l2 tag arrays reliability and serviceability ? parity checking on 60x and l2 cache buses
motorola mpc7410 risc microprocessor hardware specifications 7 general parameters 1.3 general parameters the following list provides a summary of the general parameters of the mpc7410: technology 0.18 m cmos, six-layer metal die size 6.32 mm 8.26 mm (52 mm 2 ) transistor count 10.5 million logic design fully static packages surface mount 360 ceramic ball grid array (cbga) surface mount 360 high coefficient of thermal expansion ceramic ball grid array (hcte) core power supply 1.8 v 100 mv dc (nominal; see table 3 for recommended operating conditions) i/o power supply 1.8 v 100 mv dc or 2.5 v 100 mv 3.3 v 165 mv (system bus only) (input thresholds are configuration pin selectable)
8 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics 1.4 electrical and thermal characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc7410. 1.4.1 dc electrical characteristics the tables in this section describe the mpc7410 dc electrical characteristics. table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol maximum value unit notes core supply voltage v dd ?0.3 to 2.1 v 4 pll supply voltage av dd ?0.3 to 2.1 v 4 l2 dll supply voltage l2av dd ?0.3 to 2.1 v 4 processor bus supply voltage ov dd ?0.3 to 3.6 v 3, 6 l2 bus supply voltage l2ov dd ?0.3 to 2.8 v 3 input voltage processor bus v in ?0.3 to ov dd + 0.2 v v 2, 5 l2 bus v in ?0.3 to l2ov dd + 0.2 v v 2, 5 jtag signals v in ?0.3 to ov dd + 0.2 v v storage temperature range t stg ?55 to 150 c rework temperature t rwk 260 c notes : 1. functional and tested operating conditions are given in table 3. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ov dd or l2ov dd by more than 0.2 v at any time including during power-on reset. 3. caution : l2ov dd /ov dd must not exceed v dd /av dd /l2av dd by more than 2.0 v at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution : v dd /av dd /l2av dd must not exceed l2ov dd /ov dd by more than 0.4 v at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2. 6. mpc7410rx nnn le (rev. 1.4) and later only. previous revisions do not support 3.3 v ov dd and have a maximum value ov dd of ?0.3 to 2.8 v.
motorola mpc7410 risc microprocessor hardware specifications 9 electrical and thermal characteristics figure 2 shows the allowable undershoot and overshoot voltage for the mpc7410. figure 2. overshoot/undershoot voltage the mpc7410 provides several i/o voltages to support both compatibility with existing systems and migration to future systems. the mpc7410 core voltage must always be provided at nominal voltage (see table 3 for actual recommended core voltage). voltage to the l2 i/os and processor interface i/os are provided through separate sets of supply pins and may be provided at the voltages shown in table 2. voltage must be provided to the l2ov dd power pins even if the interface is not used. the input voltage threshold for each bus is selected by sampling the state of the voltage select pins bvsel and l2vsel at the negation of the signal hreset . these signals must remain stable during part operation and cannot change. the output voltage will swing from gnd to the maximum voltage applied to the ov dd or l2ov dd power pins. table 2. input threshold voltage setting bvsel signal 3 processor bus input threshold is relative to: l2vsel signal 3 l2 bus input threshold is relative to: notes 0 1.8 v 0 1.8 v 1 hreset 2.5 v hreset 2.5 v 1, 2 1 3.3 v 1 2.5 v 1, 4, 5 ?hreset 3.3 v ?hreset not supported 6 notes: 1. caution: the input threshold selection must agree with the ov dd /l2ov dd voltages supplied. 2. to select the 2.5-v threshold option, bvsel and/or l2vsel should be tied to hreset so that the two signals change state together. this is the preferred method for selecting this mode of operation. 3. to overcome the internal pull-up resistance, a pull-down resistance less than 250 ? should be used. 4. default voltage setting if left unconnected (internal pulled-up). mpc7410rx nnn le (rev 1.4) and later only. previous revisions do not support 3.3 v ov dd , the default voltage setting if left unconnected is 2.5 v. 5. mpc7410rx nnn le (rev. 1.4) and later only. previous revisions do not support 3.3 v ov dd , having bvsel = 1 selects the 2.5-v threshold. 6. mpc7410rx nnn le (rev. 1.4) and later only. previous revisions do not support bvsel = ?hreset . (?hreset is the inverse of hreset .) v ih gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% (l2)ov dd + 20% v il (l2)ov dd (l2)ov dd + 5% of t sysclk (ov dd ) or t l2clk (l2ov dd )
10 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics table 3 provides the recommended operating conditions for the mpc7410. table 4 provides the package thermal characteristics for the mpc7410. table 3. recommended operating conditions 1 characteristic symbol recommended value unit notes core supply voltage v dd 1.8 v 100 mv v pll supply voltage av dd 1.8 v 100 mv v l2 dll supply voltage l2av dd 1.8 v 100 mv v processor bus supply voltage bvsel = 0 ov dd 1.8 v 100 mv v bvsel = hreset ov dd 2.5 v 100 mv v bvsel = ?hreset or bvsel = 1 ov dd 3.3 v 165 mv v 2, 3 l2 bus supply voltage l2vsel = 0 l2ov dd 1.8 v 100 mv v l2vsel = hreset or l2vsel = 1 l2ov dd 2.5 v 100 mv v input voltage processor bus and jtag signals v in gnd to ov dd v l2 bus v in gnd to l2ov dd v die-junction temperature t j 0 to 105 c notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. mpc7410rx nnn le (rev. 1.4) and later only. previous revisions do not support 3.3 v ov dd and have a recommended ov dd value of 2.5 v 100 mv for bvsel = 1. 3. mpc7410rx nnn le (rev. 1.4) and later only. previous revisions do not support bvsel = ?hreset . table 4. package thermal characteristics characteristic symbol value unit notes mpc7410 cbga mpc7410 hcte cbga junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 24 30 c/w 1, 2 junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r jma 17 22 c/w 1, 3 junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board r jma 18 23 c/w 1, 3 junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board r jma 16 21 c/w junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board r jma 14 19 c/w 1, 3
motorola mpc7410 risc microprocessor hardware specifications 11 electrical and thermal characteristics table 5 provides the dc electrical characteristics for the mpc7410. junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board r jma 13 18 c/w junction-to-board thermal resistance r jb 814c/w4 junction-to-case thermal resistance r jc < 0.1 < 0.1 c/w 5 notes: 1. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipat ion of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1c/w. note: refer to section 1.8.8, ?thermal management information,? for more details about thermal management. table 5. dc electrical specifications at recommended operating conditions (see table 3) characteristic nominal bus voltage 1 symbol min max unit notes input high voltage (all inputs except sysclk) 1.8 v ih 0.65 (l2)ov dd (l2)ov dd + 0.2 v 2, 3, 8 2.5 v ih 1.7 (l2)ov dd + 0.2 3.3 v ih 2.0 ov dd + 0.3 input low voltage (all inputs except sysclk) 1.8 v il ?0.3 0.35 (l2)ov dd v8 2.5 v il ?0.3 0.2 (l2)ov dd 3.3 v il ?0.3 0.8 sysclk input high voltage 1.8 cv ih 1.5 ov dd + 0.2 v 2, 8 2.5 cv ih 2.0 ov dd + 0.2 3.3 cv ih 2.4 ov dd + 0.3 sysclk input low voltage 1.8 cv il ?0.3 0.2 v 8 2.5 cv il ?0.3 0.4 3.3 cv il ?0.3 0.4 table 4. package thermal characteristics (continued) characteristic symbol value unit notes mpc7410 cbga mpc7410 hcte cbga
12 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics input leakage current, v in = l2ov dd /ov dd 1.8 i in ?20a2, 3, 6, 7 2.5 i in ?35 3.3 i in ?70 high-z (off-state) leakage current, v in = l2ov dd /ov dd 1.8 i tsi ?20a2, 3, 5, 7 2.5 i tsi ?35 3.3 i tsi ?70 output high voltage, i oh = ?6 ma 1.8 v oh (l2)ov dd ? 0.45 ? v 8 2.5 v oh 1.7 ? 3.3 v oh 2.4 ? output low voltage, i ol = 6 ma 1.8 v ol ?0.45v8 2.5 v ol ?0.4 3.3 v ol ?0.4 capacitance, v in = 0 v, f = 1 mhz c in ? 6.0 pf 3, 4, 7 notes : 1. nominal voltages; see table 3 for recommended operating conditions. 2. for processor bus signals, the reference is ov dd while l2ov dd is the reference for the l2 bus signals. 3. excludes factory test signals. 4. capacitance is periodically sampled rather than 100% tested. 5. the leakage is measured for nominal ov dd and l2ov dd , or both ov dd and l2ov dd must vary in the same direction (for example, both ov dd and l2ov dd vary by either +5% or ?5%). 6. measured at max ov dd /l2ov dd . 7. excludes ieee 1149.1 boundary scan (jtag) signals. 8. for jtag support: all signals controlled by bvsel and l2vsel will see v il /v ih /v ol /v oh /cv ih /cv il dc limits of 1.8 v mode while either the extest or clamp instruction is loaded into the ieee 1149.1 instruction register by the updateir tap state until a different instruction is loaded into the instruction register by either another updateir or a test-logic-reset tap state. if only tsrt is asserted to the part, and then a sample instruction is executed, there is no way to control or predict what the dc voltage limits are. if hreset is asserted before executing a sample instruction, the dc voltage limits will be controlled by the bvsel/l2vsel settings during hreset . anytime hreset is not asserted (that is, just asserting trst ), the voltage mode is not known until either extest or clamp is executed, at which time the voltage level will be at the dc limits of 1.8 v. table 5. dc electrical specifications (continued) at recommended operating conditions (see table 3) characteristic nominal bus voltage 1 symbol min max unit notes
motorola mpc7410 risc microprocessor hardware specifications 13 electrical and thermal characteristics table 6 provides the power consumption for the mpc7410. 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the mpc7410. after fabrication, functional parts are sorted by maximum processor core frequency, see section 1.4.2.1, ?clock ac specifications,? and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0:3] signals. parts are sold by maximum processor core frequency; see section 1.10, ?ordering information.? 1.4.2.1 clock ac specifications table 7 provides the clock ac timing specifications as defined in figure 3. table 6. power consumption for mpc7410 processor (cpu) frequency unit notes 400 mhz 450 mhz 500 mhz full-on mode typical 4.2 4.7 5.3 w 1, 3 maximum 9.5 10.7 11.9 w 1, 2 doze mode maximum 4.3 4.8 5.3 w 1 nap mode maximum 1.35 1.5 1.65 w 1 sleep mode maximum 1.3 1.45 1.6 w 1 sleep mode?pll and dll disabled typical 600 600 600 mw 1 maximum 1.1 1.1 1.1 w 1 notes: 1. these values apply for all valid processor bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically <5% of v dd power. worst case power consumption for av dd = 15 mw and l2av dd =15 mw. 2. maximum power is measured at 105c and v dd = 1.8 v while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including altivec, maximally busy. 3. typical power is an average value measured at 65c and v dd = 1.8 v in a system while running typical benchmarks.
14 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics figure 3 provides the sysclk input timing diagram. figure 3. sysclk input timing diagram table 7. clock ac timing specifications at recommended operating conditions (see table 3) characteristic symbol maximum processor core frequency unit notes 400 mhz 450 mhz 500 mhz min max min max min max processor frequency f core 350 400 350 450 350 500 mhz 1 vco frequency f vco 700 800 700 900 700 1000 mhz 1 sysclk frequency f sysclk 33 133 33 133 33 133 mhz 1 sysclk cycle time t sysclk 7.5307.5307.530 ns sysclk rise and fall time t kr and t kf ? 0.5 ? 0.5 ? 0.5 ns/v 2 sysclk duty cycle measured at ov dd /2 t khkl /t sysclk 40 60 40 60 40 60 % 3 sysclk jitter ? 150 ? 150 ? 150 ps 4 internal pll-relock time ? 100 ? 100 ? 100 s5 notes : 1. caution : the sysclk frequency and pll_cfg[0:3] settings mu st be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:3] signal description in section 1.8.1, ?pll configuration,? for valid pll_cfg[0:3] settings. 2. rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. as a result, the 0.5 ns rise/fall time spec of the 1.8- and 2.5-v bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-v bus interface. both interfaces required a 2 v/ns slew rate. the slew rate is measured as a 1-v change (from 0.2 to 1.2 v) in 0.5 ns for the 1.8- and 2.5-v bus interfaces, whereas the 3.3-v bus interface required a 2-v change (from 0.4 to 2.4 v) in 1 ns. 3. timing is guaranteed by design and characterization. 4. this represents total input jitter?short- and long-term combined?and is guaranteed by design. 5. relock timing is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. sysclk vm vm vm cv ih cv il vm = midpoint voltage (ov dd /2) t sysclk t kr t kf t khkl
motorola mpc7410 risc microprocessor hardware specifications 15 electrical and thermal characteristics 1.4.2.2 processor bus ac specifications table 8 provides the processor bus ac timing specifications for the mpc7410 as defined in figure 4 and figure 5. timing specifications for the l2 bus are provided in section 1.4.2.3, ?l2 clock ac specifications.? table 8. processor bus ac timing specifications 1 at recommended operating conditions (see table 3) parameter symbol 2 400, 450, 500 mhz unit notes min max input setup t ivkh 1.0 ? ns 4 input hold t ixkh 0?ns4 output valid times: ts artry , shd0 , shd1 all other outputs t khtsv t kharv t khov ? ? ? 3.0 2.3 3.0 ns 5, 6 output hold times: ts artry , shd0 , shd1 all other outputs t khtsx t kharx t khox 0.5 0.5 0.5 ? ? ? ns 5 sysclk to output enable t khoe 0.5 ? ns 9 sysclk to output high impedance (all except abb /amon (0), artry /shd , dbb /dmon (0), shd0 , shd1 ) t khoz ?3.5ns sysclk to abb /amon (0), dbb /dmon (0) high impedance after precharge t khabpz ?1t sysclk 3, 7, 9 maximum delay to artry , shd0 , shd1 precharge t kharp ?1t sysclk 3, 8, 9
16 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics figure 4 provides the ac test load for the mpc7410. figure 4. ac test load sysclk to artry , shd0 , shd1 high impedance after precharge t kharpz ?2t sysclk 3, 8, 9 notes: 1. all input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are measured from the midpoint of the rising edge of sysclk to the midpoint of the signal in question. all output timings assume a purely resistive 50- ? load (see figure 4). input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbology used for timing specifications herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the high (h) state or input setup time. and t khov symbolizes the time from sysclk(k) going high (h) until outputs (o) are valid (v) or output valid time. input hold time can be read as the time that the input signal (i) went invalid (x) with respect to the rising clock edge (kh)? note the position of the reference and its state for inputs?and output hold time can be read as the time from the rising edge (kh) until the output went invalid (ox). 3. t sysclk is the period of the external clock (sysclk) in ns. the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. includes mode select signals: bvsel, emode, l2vsel. see figure 5 for mode select timing with respect to hreset . 5. all other output signals are composed of the following? a[0:31], ap[0:3], tt[0:4], ts, tbst , tsiz[0:2], gbl , wt , ci , dh[0:31], dl[0:31], dp[0:7], br , ckstp_out , drdy , hit , qreq , rsrv . 6. output valid time is measured from 2.4 to 0.8 v which ma y be longer than the time required to discharge from v dd to 0.8 v. 7. according to the 60x bus protocol, abb and dbb are driven only by the currently active bus master. they are asserted low then precharged high before returning to high-z as shown in figure 6. the nominal precharge width for abb or dbb is 0.5 t sysclk , that is, less than the minimum t sysclk period, to ensure that another master asserting abb , or dbb on the following clock will not contend with the precharge. output valid and output hold timing is tested for the signal asserted. output valid time is tested for precharge.the high-z behavior is guaranteed by design. 8. according to the 60x bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue since any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high-z for one clock before precharging it high during the second cycle after the assertion of aack . the nominal precharge width for artry is 1.0 t sysclk ; that is, it should be high-z as shown in figure 6 before the first opportunity for another master to assert artry . output valid and output hold timing are tested for the signal asserted. output valid time is tested for precharge. the high-z behavior is guaranteed by design. 9. guaranteed by design and not tested. table 8. processor bus ac timing specifications 1 (continued) at recommended operating conditions (see table 3) parameter symbol 2 400, 450, 500 mhz unit notes min max output z 0 = 50 ? ov dd /2 r l = 50 ?
motorola mpc7410 risc microprocessor hardware specifications 17 electrical and thermal characteristics figure 5 provides the mode select input timing diagram for the mpc7410. the mode select inputs are sampled twice, once before and once after hreset negation. figure 5. mode input timing diagram figure 6 provides the input/output timing diagram for the mpc7410. figure 6. input/output timing diagram hreset mode signals vm = midpoint voltage (ov dd /2) sysclk first sample second sample vm vm sysclk all inputs vm vm = midpoint voltage (ov dd /2) all outputs t khox vm (except ts , abb , artry , dbb ) all outputs ts , artry , abb /amon (0), (except ts , abb , artry , dbb ) dbb /dmon (0) vm t khoe t khoz t khabpz t kharpz t kharp shd1 shd0 , t khov t ixkh t khtsx t khtsv t khtsv t kharv t kharx t kharv t ivkh
18 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics 1.4.2.3 l2 clock ac specifications the l2clk frequency is programmed by the l2 configuration register (l2cr[4:6]) core-to-l2 divisor ratio. see table 14 for example core and l2 frequencies at various divisors. table 9 provides the potential range of l2clk output ac timing specifications as defined in figure 7. the l2sync_out signal is intended to be routed halfway out to the srams and then returned to the l2sync_in input of the mpc7410 to synchronize l2clk_out at the sram with the processor?s internal clock. l2clk_out at the sram can be offset forward or backward in time by shortening or lengthening the routing of l2sync_out to l2sync_in. see motorola application note an1794/d, backside l2 timing analysis for the pcb design engineer . the minimum l2clk frequency in table 9 is specified by the maximum delay of the internal dll. the variable-tap dll introduces up to a full clock period delay in the l2clk_outa, l2clk_outb, and l2sync_out signals so that the returning l2sync_in signal is phase-aligned with the next core clock (divided by the l2 divisor ratio). do not choose a core-to-l2 divisor which results in an l2 frequency below this minimum, or the l2clk_out signals provided for sram clocking will not be phase-aligned with the mpc7410 core clock at the srams. the maximum l2clk frequency shown in table 9 is the core frequency divided by one. very few l2 sram designs will be able to operate in this mode. most designs will select a greater core-to-l2 divisor to provide a longer l2clk period for read and write access to the l2 srams. the maximum l2clk frequency for any application of the mpc7410 will be a function of the ac timings of the mpc7410, the ac timings for the sram, bus loading, and printed-circuit board trace length. motorola is similarly limited by system constraints and cannot perform tests of the l2 interface on a socketed part on a functional tester at the maximum frequencies in table 9. therefore, functional operation and ac timing information are tested at core-to-l2 divisors of two or greater. l2 input and output signals are latched or enabled, respectively, by the internal l2clk (which is sysclk multiplied up to the core frequency and divided down to the l2clk frequency). in other words, the ac timings in table 10 are entirely independent of l2sync_in. in a closed loop system, where l2sync_in is driven through the board trace by l2sync_out, l2sync_in only controls the output phase of l2clk_outa and l2clk_outb which are used to latch or enable data at the srams. however, since in a closed loop system l2sync_in is held in phase-alignment with the internal l2clk, the signals in table 10 are referenced to this signal rather than the not-externally-visible internal l2clk. during manufacturing test, these times are actually measured relative to sysclk. table 9. l2clk output ac timing specifications at recommended operating conditions (see table 3) parameter symbol 400 mhz 450 mhz 500 mhz unit notes min max min max min max l2clk frequency f l2clk 133 400 133 400 133 400 mhz 1, 4 l2clk cycle time t l2clk 2.5 7.5 2.5 7.5 2.5 7.5 ns l2clk duty cycle t chcl /t l2clk 50 50 50 % 2 internal dll-relock time 640 ? 640 ? 640 ? l2clk 3 dll capture window 0 10 0 10 0 10 ns 5 l2clk_out output-to-output skew t l2cskw ?50?50?50ps 6
motorola mpc7410 risc microprocessor hardware specifications 19 electrical and thermal characteristics the l2clk_out timing diagram is shown in figure 7. figure 7. l2clk_out output timing diagram l2clk_out output jitter ? 150 ? 150 ? 150 ps 6 notes : 1. l2clk outputs are l2clk_outa, l2clk_outb, and l2sync_out pins. the l2clk frequency to core frequency settings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. the maximum l2clk frequency will be system dependent. l2clk_outa and l2clk_outb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measured at midpoint voltage. 3. the dll-relock time is specified in terms of l2clks. the number in the table must be multiplied by the period of l2clk to compute the actual time duration in ns. relock timing is guaranteed by design and characterization. 4. the l2cr[l2sl] bit should be set for l2clk frequencies less than 150 mhz. this adds more delay to each tap of the dll. 5. allowable skew between l2sync_out and l2sync_in. 6. guaranteed by design and not tested. this output jitter number represents the maximum delay of one tap forward or one tap back from the current dll tap as the phase comparator seeks to minimize the phase difference between l2sync_in and the internal l2clk. this number must be comprehended in the l2 timing analysis. the input jitter on sysclk affects l2clk_out and the l2 address/data/c ontrol signals equally and, therefore, is already comprehended in the ac timing and does not have to be considered in the l2 timing analysis. table 9. l2clk output ac timing specifications (continued) at recommended operating conditions (see table 3) parameter symbol 400 mhz 450 mhz 500 mhz unit notes min max min max min max vm = midpoint voltage (l2o v dd /2) l2clk_outa l2clk_outb l2 differential clock mode l2 single-ended clock mode l2sync_out t l2clk t chcl l2clk_outa vm t l2cr t l2cf vm vm vm l2clk_outb vm vm vm vm vm t l2clk t chcl l2sync_out vm vm vm vm vm vm vm vm t l2cskw vm
20 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics 1.4.2.4 l2 bus ac specifications table 10 provides the l2 bus interface ac timing specifications for the mpc7410 as defined in figure 8 and figure 9 for the loading conditions described in figure 10. table 10. l2 bus interface ac timing specifications at recommended operating conditions (see table 3) parameter symbol 400, 450, 500 mhz unit notes min max l2sync_in rise and fall time t l2cr and t l2cf ?1.0ns1 setup times: data and parity t dvl2ch 1.5 ? ns 2 input hold times: data and parity t dxl2ch ?0.0ns2 valid times: all outputs when l2cr[14?15] = 00 all outputs when l2cr[14?15] = 01 all outputs when l2cr[14?15] = 10 all outputs when l2cr[14?15] = 11 t l2chov ? ? ? ? 2.5 2.5 2.9 3.5 ns 3, 4 output hold times all outputs when l2cr[14?15] = 00 all outputs when l2cr[14?15] = 01 all outputs when l2cr[14?15] = 10 all outputs when l2cr[14?15] = 11 t l2chox 0.4 0.8 1.2 1.6 ? ? ? ? ns 3 l2sync_in to high impedance: all outputs when l2cr[14?15] = 00 all outputs when l2cr[14?15] = 01 all outputs when l2cr[14?15] = 10 all outputs when l2cr[14?15] = 11 t l2choz ? ? ? ? 2.0 2.5 3.0 3.5 ns notes : 1. rise and fall times for the l2sync_in input are measured from 20% to 80% of l2ov dd . 2. all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input l2sync_in (see figure 8). input timings are measured at the pins. 3. all output specifications are measured from the midpoint voltage of the rising edge of l2sync_in to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- ? load (see figure 10). 4. the outputs are valid for both single-ended and differential l2clk modes. for pipelined registered synchronous burstrams, l2cr[14?15] = 00 is recommended. for pipelined late write synchronous burstrams, l2cr[14?15] = 10 is recommended.
motorola mpc7410 risc microprocessor hardware specifications 21 electrical and thermal characteristics figure 8 shows the l2 bus input timing diagrams for the mpc7410. figure 8. l2 bus input timing diagrams figure 9 shows the l2 bus output timing diagrams for the mpc7410. figure 9. l2 bus output timing diagrams figure 10 provides the ac test load for l2 interface of the mpc7410. figure 10. ac test load for the l2 interface 1.4.2.5 ieee 1149.1 ac timing specifications table 11 provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 12 through figure 15. table 11. jtag ac timing specifica tions (independent of sysclk) 1 at recommended operating conditions (see table 3) parameter symbol min max unit notes tck frequency of operation f tclk 033.3mhz tck cycle time t tclk 30 ? ns tck clock pulse width measured at ov dd /2 t jhjl 15 ? ns tck rise and fall times t jr and t jf 02ns l2sync_in vm vm = midpoint voltage (l2ov dd /2) t dvl2ch t dxl2ch t l2cr t l2cf l2 data and inputs data parity l2sync_in all outputs vm vm = midpoint voltage (l2ov dd /2) t l2chov t l2chox vm l2data bus t l2choz output z 0 = 50 ? l2ov dd / 2 r l = 50 ?
22 mpc7410 risc microprocessor hardware specifications motorola electrical and thermal characteristics electrical and thermal characteristics figure 11 provides the ac test load for tdo and the boundary-scan outputs of the mpc7410. figure 11. alternate ac test load for the jtag interface figure 12 provides the jtag clock input timing diagram. figure 12. jtag clock input timing diagram figure 13 provides the trst timing diagram. figure 13. trst timing diagram trst assert time t trst 25 ? ns 2 input setup times: boundary-scan data tms, tdi t dvjh t ivjh 4 0 ? ? ns 3 input hold times: boundary-scan data tms, tdi t dxjh t ixjh 20 25 ? ? ns 3 valid times: boundary-scan data tdo t jldv t jlov 4 4 20 25 ns 4 tck to output high impedance: boundary-scan data tdo t jldz t jloz 3 3 19 9 ns 4, 5 5 notes : 1. all outputs are measured from the midpoint voltage of the falling/rising edge of tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- ? load (see figure 11). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 3. non-jtag signal input timing with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization. table 11. jtag ac timing specifications (independent of sysclk) 1 (continued) at recommended operating conditions (see table 3) parameter symbol min max unit notes output z 0 = 50 ? ov dd / 2 r l = 50 ? tclk vm vm vm vm = midpoint voltage (ov dd /2) t tclk t jr t jf t jhjl trst t trst vm = midpoint voltage (ov dd /2) vm vm
motorola mpc7410 risc microprocessor hardware specifications 23 electrical and thermal characteristics figure 14 provides the boundary-scan timing diagram. figure 14. boundary-scan timing diagram figure 15 provides the test access port timing diagram. figure 15. test access port timing diagram vm tck boundary boundary boundary d ata outputs data inputs d ata outputs vm = midpoint voltage (ov dd /2) t dxjh t dvjh t jldv t jldz input data valid output data valid output data valid t jldx vm vm tck tdi, tms tdo output data valid vm = midpoint voltage (ov dd /2) t ixjh t ivjh t jlov t jloz input data valid tdo output data valid t jlox vm
24 mpc7410 risc microprocessor hardware specifications motorola pin assignments pin assignments 1.5 pin assignments figure 16 (in part a) shows the pinout for both the mpc7410, 360 cbga and 360 hcte packages as viewed from the top surface. part b shows the side profile of the package to indicate the direction of the top surface view. figure 16. pinout of the mpc7410, 360 cbga and 360 hcte packages as viewed from the top surface a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 not to scale 17 18 19 u v w part a view part b die substrate assembly encapsulant
motorola mpc7410 risc microprocessor hardware specifications 25 pinout listings 1.6 pinout listings table 12 provides the pinout listing for the mpc7410, 360 cbga and 360 hcte packages. table 12. pinout listing for the mpc7410, 360 cbga and 360 hcte packages signal name pin number active i/o i/f select 1 notes a[0:31] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o bvsel aack n3 low input bvsel abb l7 low output bvsel 12, 16 ap[0:3] c4, c5, c6, c7 high i/o bvsel artry l6 low i/o bvsel av dd a8 ? input v dd bg h1 low input bvsel br e7 low output bvsel bvsel w1 high input n/a 1, 3, 8, 9, 14 chk k11 low input bvsel 2, 8, 9 ci c2 low i/o bvsel ckstp_in b8 low input bvsel ckstp_out d7 low output bvsel clk_out e3 high output bvsel dbb k5 low output bvsel 12, 16 dbg k1 low input bvsel dh[0:31] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o bvsel dl[0:31] m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o bvsel dp[0:7] l1, p2, m2, v2, m1, n2, t3, r1 high i/o bvsel drdy k9 low output bvsel 6, 8, 13 dbwo dti[0] d1 low input bvsel dti[1:2] h6, g1 high input bvsel 5, 10, 13 emode a3 low input bvsel 7, 10
26 mpc7410 risc microprocessor hardware specifications motorola pinout listings pinout listings gbl b1 low i/o bvsel gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 ?? n/a hit b5 low output bvsel 6, 8 hreset b6 low input bvsel int c11 low input bvsel l1_tstclk f8 high input bvsel 2 l2addr[0:16] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2vsel l2addr[17:18] k19,w19 high output l2vsel 8 l2av dd l13 ? input v dd l2ce p17 low output l2vsel l2clk_outa n15 high output l2vsel l2clk_outb l16 high output l2vsel l2data[0:63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o l2vsel l2dp[0:7] v14, u16, t19, n18, h14, f17, c19, b15 high i/o l2vsel l2ov dd d15, e14, e16, h16, j15, l15, m16, k13, p15, r14, r16, t15, f15 ?? n/a11 l2sync_in l14 high input l2vsel l2sync_out m14 high output l2vsel l2_tstclk f7 high input bvsel 2 l2vsel a19 high input n/a 1, 3, 8, 9, 14 l2we n16 low output l2vsel l2zz g17 high output l2vsel lssd_mode f9 low input bvsel 2 table 12. pinout listing for the mpc7410, 360 cbga and 360 hcte packages (continued) signal name pin number active i/o i/f select 1 notes
motorola mpc7410 risc microprocessor hardware specifications 27 pinout listings mcp b11 low input bvsel 15 ov dd d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 ?? n/a pll_cfg[0:3] a4, a5, a6, a7 high input bvsel 4 qack b2 low input bvsel qreq j3 low output bvsel rsrv d3 low output bvsel shd0 b3 low i/o bvsel 8 shd1 b4 low i/o bvsel 5, 8 smi a12 low input bvsel sreset e10 low input bvsel sysclk h9 ? input bvsel ta f1 low input bvsel tben a2 high input bvsel tbst a11 low output bvsel tck b10 high input bvsel tdi b7 high input bvsel 9 tdo d9 high output bvsel tea j1 low input bvsel tms c8 high input bvsel 9 trst a10 low input bvsel 9 ts k7 low i/o bvsel tsiz[0:2] a9, b9, c9 high output bvsel tt[0:4] c10, d11, b12, c12, f11 high i/o bvsel wt c3 low i/o bvsel table 12. pinout listing for the mpc7410, 360 cbga and 360 hcte packages (continued) signal name pin number active i/o i/f select 1 notes
28 mpc7410 risc microprocessor hardware specifications motorola pinout listings pinout listings v dd g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 ?? n/a notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals except the l2 cache controls (l2ce , l2we , and l2zz); l2ov dd supplies power to the l2 cache interface (l2addr[0:18], l2data[0:63], l2dp[0:7], and l2sync_out) and the l2 control signals; and v dd supplies power to the processor core and the pll and dll (after filtering to become av dd and l2av dd , respectively). these columns serve as a reference for the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin configurations of table 2 and the voltage supplied. for actual recommended value of v in or supply voltages, see table 3. 2. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 3. to allow for future i/o voltage changes, provide the option to connect bvsel and l2vsel independently to either ov dd , gnd, hreset , or ?hreset . for the mpc7410 the l2 bus only supports 2.5- and 1.8-v options. the default selection, if l2vsel is left unconnected, is 2.5- v operation. for the mpc7410 the processor bus supports 3.3-, 2.5-, and 1.8-v options. the default selection, if bvsel is left unconnected, is 3.3-v operation. refer to table 2 for supported bvsel and l2vsel settings. 4. pll_cfg[0:3] must remain stable during operation; should only be changed during the assertion of hreset or during sleep mode and must adhere to the internal pll-relock time requirement. 5. ignored input in 60x bus mode. 6. unused output in 60x bus mode. signal is three-stated in 60x mode. 7. deasserted (pulled high) at hreset negation for 60x bus mode. asserted (pulled low) at hreset negation for mpx bus mode. 8. uses one of nine existing no connects in the mpc750 360 bga package. 9. internal pull up on die. pulled-up signals are v dd based. 10. reuses mpc750 drtry , dbdis , and tlbisync pins (dti1, dti2, and emode , respectively). 11. the voltdet pin position on the mpc750 360 cbga package is now an l2ov dd pin on the mpc7410 360 cbga package. 12. output only for mpc7410, was i/o for mpc750. 13. mpx bus mode only. 14. if necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250 ? should be used. 15. mcp minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to guarantee that it is latched by the processor. 16. in mpx bus mode the abb signal is called amon and the dbb signal is called dmon . these signals are not a requirement of the mpx bus protocol and may not be available on future products. table 12. pinout listing for the mpc7410, 360 cbga and 360 hcte packages (continued) signal name pin number active i/o i/f select 1 notes
motorola mpc7410 risc microprocessor hardware specifications 29 package description 1.7 package description the following sections provide the package parameters and mechanical dimensions for both the mpc7410, 360 cbga and 360 hcte packages. 1.7.1 package parameters for the mpc7410 the package parameters are as provided in the following list. the package types are the 25 25 mm, 360-lead ceramic ball grid array package (cbga) or the 25 25 mm, 360-lead high coefficient of thermal expansion cbga package (hcte). package outline 25 25 mm interconnects 360 (19 19 ball array ? 1) pitch 1.27 mm (50 mil) minimum module height 2.65 mm maximum module height 3.20 mm ball diameter 0.89 mm (35 mil) 1.7.2 mechanical dimensions for the mpc7410 figure 17 provides the mechanical dimensions and bottom surface nomenclature of the mpc7410, 360 cbga and 360 hcte packages.
30 mpc7410 risc microprocessor hardware specifications motorola package description package description figure 17. mechanical dimensions and bottom surface nomenclature for the mpc7410, 360 cbga and 360 hcte packages notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. 0.2 d 2x a1 corner e e2 d2 0.2 2x b a millimeters dim min max a 2.72 3.20 a1 0.80 1.00 a2 1.10 1.30 a3 ? 0.60 a4 0.82 0.90 b 0.82 0.93 d 25.00 bsc d2 ? 12.50 d4 6.00 7.30 e 1.27 bsc e 25.00 bsc e2 ? 14.30 e4 8.00 9.70 k1 8.92 9.12 k2 6.46 6.66 k3 8.20 8.60 l1 9.40 9.60 l2 6.94 7.14 l3 3.10 3.30 a a1 a2 c 0.15 c e4 d4 b c 360x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b 171819 u w v 0.25 c // 0.35 c // a3 a4 k1 k2 l1 l2 k3 l3 capacitor region
motorola mpc7410 risc microprocessor hardware specifications 31 system design information 1.7.3 substrate capacitors for the mpc7410 figure 18 shows the connectivity of the substrate capacitor pads for the mpc7410, 360 cbga and 360 hcte packages. figure 18. substrate bypass capacitors for the mpc7410 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the mpc7410. 1.8.1 pll configuration the mpc7410 pll is configured by the pll_cfg[0:3] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the mpc7410 is shown in table 13 for example frequencies. in this example, shaded cells represent settings that, for a given sysclk frequency, result in core and/or vco frequencies that do not comply with the minimum and maximum core frequencies listed in table 8. table 13. mpc7410 microprocessor pll configuration pll_cfg [0:3] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 33.3 mhz bus 50 mhz bus 66.6 mhz bus 75 mhz bus 83.3 mhz bus 100 mhz bus 133 mhz 0100 2x 2x 0110 2.5x 2x 1000 3x 2x 400 (800) 1110 3.5x 2x 350 (700) 465 (930) 1010 4x 2x 400 (800) package caps value f voltage reference c1-1 0.01 l2ov dd c1-2 gnd c2-1 0.01 l2ov dd c2-2 gnd c3-1 0.01 v dd c3-2 gnd c4-1 0.01 ov dd c4-2 gnd c5-1 0.01 ov dd c5-2 gnd c6-1 0.01 v dd c6-2 gnd a1 corner c1-1 c1-2 c2-1 c2-2 c3-2 c3-1 c4-2 c4-1 c5-2 c5-1 c6-1 c6-2 l1 l2
32 mpc7410 risc microprocessor hardware specifications motorola system design information system design information the mpc7410 generates the clock for the external l2 synchronous data srams by dividing the core clock frequency of the mpc7410. the divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (dll) circuit and should be routed from the mpc7410 to the external rams. a separate clock output, l2sync_out is sent out half the distance to the srams and then returned as an input to the dll on pin l2sync_in so that the rising-edge of the clock as seen at the external rams can be aligned to the clocking of the internal latches in the l2 bus interface. the core-to-l2 frequency divisor for the l2 pll is selected through the l2clk bits of the l2cr register. generally, the divisor must be chosen according to the frequency supported by the external rams, the frequency of the mpc7410 core, and the phase adjustment range that the l2 dll supports. table 14 shows 0111 4.5x 2x 375 (750) 450 (900) 1011 5x 2x 375 (750) 416 (833) 500 (1000) 1001 5.5x 2x 366 (733) 412 (825) 458 (916) 1101 6x 2x 400 (800) 450 (900) 500 (1000) 0101 6.5x 2x 433 (866) 488 (967) 0010 7x 2x 350 (700) 466 (933) 0001 7.5x 2x 375 (750) 500 (1000) 1100 8x 2x 400 (800) 0000 9x 2x 450 (900) 0011 pll off/bypass pll off, sysclk clocks core circuitry directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs notes: 1. pll_cfg[0:3] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not supported, or not tested for by the mpc7410; see section 1.4.2.1, ?clock ac specifications,? for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use and third-party emulator tool development only. note : the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in pll-off mode, no clocking occurs inside the mpc7410 regardless of the sysclk input. 5. pll-off mode should not be used during chip power-up sequencing. table 13. mpc7410 microprocessor pll configuration (continued) pll_cfg [0:3] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 33.3 mhz bus 50 mhz bus 66.6 mhz bus 75 mhz bus 83.3 mhz bus 100 mhz bus 133 mhz
motorola mpc7410 risc microprocessor hardware specifications 33 system design information various example l2 clock frequencies that can be obtained for a given set of core frequencies. the minimum l2 frequency target is 133 mhz. sample core-to-l2 frequencies for the mpc7410 is shown in table 14. in this example, shaded cells represent settings that, for a given core frequency, result in l2 frequencies that do not comply with the minimum and maximum l2 frequencies listed in table 10. 1.8.2 pll and dll power supply filtering the av dd and l2av dd power signals are provided on the mpc7410 to supply power to the pll and dll, respectively. on systems that use the mpc7410 cbga device, the l2av dd filter should implement the circuit shown in figure 19. the av dd filter on the mpc7410 cbga device should implement the circuit shown in figure 20. on systems that use the mpc7410 hcte device, the av dd and l2av dd input signals should both implement the circuit shown in figure 19. the circuit shown below should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. a separate circuit should be placed as close as possible to the l2av dd pin. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 360 cbga footprint, without the inductance of vias. the l2av dd pin may be more difficult to route, but is proportionately less critical. it is the recommendation of motorola, that systems that implement the av dd filter shown in figure 20 design in the pads for the removed capacitors (shown in figure 19), to provide for the possible reintroduction of the filter in figure 19. this would be necessary in case there is a planned transition to the hcte package of the mpc7410. table 14. sample core-to-l2 frequencies core frequency (mhz) 1 1.5 2 2.5 3 3.5 4 350 350 233 175 140 ? ? ? 366 366 244 183 147 ? ? ? 400 400 266 200 160 133 ? ? 433 ? 288 216 173 144 ? ? 450 ? 300 225 180 150 ? ? 466 ? 311 233 186 155 133 ? 500 ? 333 250 200 166 143 ? note: the core and l2 frequencies are for reference only. some examples may represent core or l2 frequencies which are not useful, not supported, or not tested for by the mpc7410; see section 1.4.2.3, ?l2 clock ac specifications,? for valid l2clk frequencies. the l2cr[l2sl] bit should be set for l2clk frequencies less than 150 mhz.
34 mpc7410 risc microprocessor hardware specifications motorola system design information system design information figure 19. pll power supply filter circuit no.1 figure 20. pll power supply filter circuit no. 2 1.8.3 decoupling recommendations due to the mpc7410 dynamic power management feature, large address and data buses, and high operating frequencies, the mpc7410 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc7410 system, and the mpc7410 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , and l2ov dd pin of the mpc7410. it is also recommended that these decoupling capacitors receive their power from separate v dd , (l2)ov dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations, where connections are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , l2ov dd , and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 1.8.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level through a resistor. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , l2ov dd , and gnd pins of the mpc7410. note that power must be supplied to l2ov dd even if the l2 interface of the mpc7410 will not be used; the remainder of the l2 interface may be left unterminated. v dd av dd (or l2av dd ) 10 ? 2.2 f 2.2 f gnd low esl surface mount capacitor s v dd av dd 51 ? gnd capacitor pad sites
motorola mpc7410 risc microprocessor hardware specifications 35 system design information 1.8.5 output buffer dc impedance the mpc7410 60x and l2 i/o drivers are characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 21). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals (l2)ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals (l2)ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 21 describes the driver impedance measurement circuit described above. figure 21. driver impedance measurement circuit alternately, the following is another method to determine the output impedance of the mpc7410. a voltage source, v force , is connected to the output of the mpc7410, as in figure 22. data is held low, the voltage source is set to a value that is equal to (l2)ov dd /2, and the current sourced by v force is measured. the voltage drop across the pull-down device, which is equal to (l2)ov dd /2, is divided by the measured current to determine the output impedance of the pull-down device, r n . similarly, the impedance of the pull-up device is determined by dividing the voltage drop of the pull-up, (l2)ov dd /2, by the current sank by the pull-up when the data is high and v force is equal to (l2)ov dd /2. this method can be employed with either empirical data from a test setup or with data from simulation models, such as ibis. ov dd ognd r p r n pad data sw1 sw2
36 mpc7410 risc microprocessor hardware specifications motorola system design information system design information r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 22 describes the alternate driver impedance measurement circuit. figure 22. alternate driver impedance measurement circuit table 15 summarizes the signal impedance results. the driver impedance values were characterized at 0, 65, and 105c. the impedance increases with junction temperature and is relatively unaffected by bus voltage. 1.8.6 pull-up resistor requirements the mpc7410 requires pull-up resistors (1 k ? ?5 k ? ) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the mpc7410 or other bus masters. these pins are: ts , artry , shdo , shd1 . four test pins also require pull-up resistors (100 ?? 1k ?) . these pins are chk , l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ov dd for normal machine operation. if pull-down resistors are used to configure bvsel or l2vsel, the resistors should be less than 250 ? (see table 12). because pll_cfg[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k ? or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. in addition, ckstp_out is an open-drain style output that requires a pull-up resistor (1 k ? ?5 k ? ) if it is used by the system. the ckstp_in signal should likewise be pulled up through a pull-up resistor (1 k ? ?5 k ? ) to prevent erroneous assertions of this signal. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. since the mpc7410 must continually monitor these signals for snooping, this float condition may cause excessive power draw table 15. impedance characteristics v dd = 1.8 v, ov dd = 2.5 v, t j = 0 ? 105c impedance processor bus l2 bus symbol unit r n 41.5?54.3 42.7?54.1 z 0 ? r p 37.3?55.3 39.3?50.0 z 0 ? (l2)ov dd bga data pin v forc e ognd
motorola mpc7410 risc microprocessor hardware specifications 37 system design information by the input receivers on the mpc7410 or by other receivers in the system. these signals can be pulled up through weak (10-k ? ) pull-up resistors by the system, address bus driven mode can be enabled (see the mpc7410 risc microprocessor family users? manual for more information on this mode), or these signals may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw. the snooped address and transfer attribute inputs are: a[0:31], ap[0:3], tt[0:4], ci , wt , and gbl . in systems where gbl is not connected and other devices may be asserting ts for a snoopable transaction while not driving gbl to the processor, we recommend that a strong (1 k ? ) pull-up resistor be used on gbl . note that the mpc7410 will only snoop transactions when gbl is asserted. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. the data bus signals are: dh[0:31], dl[0:31], and dp[0:7]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. if parity checking is disabled through hid0, and parity generation is not required by the mpc7410 (note that the mpc7410 always generates parity), then all parity pins may be left unconnected by the system. the l2 interface does not normally require pull-up resistors. 1.8.7 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 23 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0- ? isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during power-on. while motorola recommends that the cop header be designed into the system as shown in figure 23, if this is not possible, the isolation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 23 adds many benefits?breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface?and can be as inexpensive as an unpopulated footprint for a header to be added when needed.
38 mpc7410 risc microprocessor hardware specifications motorola system design information system design information figure 23. cop connector diagram hreset hreset 6 from target board sources hreset 13 sreset sreset sreset nc nc 11 vdd_sense 6 5 1 15 2 k ? 10 k ? 10 k ? 10 k ? ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 key qack ov dd ov dd 10 k ? ov dd 10 k ? ov dd 10 k ? 10 k ? qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k ? 4 ov dd 1 2 k ? 3 0 ? 5 notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented on the mpc7410. connect pin 5 of the cop header to ov dd with a 10-k ? pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drain type output and does not actively deassert qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag interface is not implemented, connect hreset from the target source to trst of the part through a 0- ? isolation reisistor. 6. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. trst 6 10 k ? ov dd
motorola mpc7410 risc microprocessor hardware specifications 39 system design information the cop interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 23; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 23 is common to all known emulators. the qack signal shown in figure 23 is usually connected to the pci bridge chip in a system and is an input to the mpc7410 informing it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the mpc7410 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additionally, some emulator products implement open-drain type outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutually exclusive and it is never necessary to populate both in a system. to preserve correct power-down operation, qack should be merged via logic so that it also can be driven by the pci bridge. 1.8.8 thermal management information this section provides thermal management information for the mpc7410 for air-cooled applications. proper thermal control design is primarily dependent on the system-level design?the heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see figure 24. this spring force should not exceed 5.5 pounds of force. note that care should be taken to avoid focused forces being applied to die corners and/or edges when mounting heat sinks. figure 24. package exploded cross-sectional view with several heat sink options adhesive or thermal interface material heat sink cbga package heat sink clip printed-circuit board option
40 mpc7410 risc microprocessor hardware specifications motorola system design information system design information the board designer can choose between several types of heat sinks to place on the mpc7410. there are several commercially-available heat sinks for the mpc7410 provided by the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com tyco electronics 800-522-6752 chip coolers tm p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5201 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.8.1 internal package conduction resistance for the exposed-die packaging technology, shown in table 3, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (or top-of-die for exposed silicon) thermal resistance the die junction-to-ball thermal resistance figure 25 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms.
motorola mpc7410 risc microprocessor hardware specifications 41 system design information figure 25. c4 package with heat sink mounted to a printed-circuit board 1.8.8.2 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 26 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 24). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 26 describes the thermal performance of selected thermal interface materials. external resistance external resistance internal resistance note the internal versus external package resistance. radiation convection radiation convection heat sink printed-circuit board thermal interface materia l package/leads die junction die/package
42 mpc7410 risc microprocessor hardware specifications motorola system design information system design information figure 26. thermal performance of select thermal interface material the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon court woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dow.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006") bare joint floroether oil sheet (0.007") graphite/oil sheet (0.005") synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
motorola mpc7410 risc microprocessor hardware specifications 43 system design information 1.8.8.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) p d where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value specified in table 3. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10c. the thermal resistance of the thermal interface material ( int ) is typically about 1c/w. assuming a t a of 30c, a t r of 5c, a cbga package jc = 0.03, and a power consumption (p d ) of 5.0 w, the following expression for t j is obtained: die-junction temperature: t j = 30c + 5c + (0.03c/w + 1.0c/w + sa ) 5.0 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity is shown in figure 27. assuming an air velocity of 0.5 m/s, we have an effective r sa of 7c/w, thus t j = 30c + 5c + (0.03c/w + 1.0c/w + 7c/w) 5.0 w, resulting in a die-junction temperature of approximately 75c which is well within the maximum operating temperature of the component. other heat sinks offered by aavid thermalloy, alpha novatech, the bergquist company, ierc, chip coolers, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow.
44 mpc7410 risc microprocessor hardware specifications motorola system design information system design information figure 27. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature?airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. 1 3 5 7 8 00.511.522.533. 5 thermalloy #2328b pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance (oc/w) (25 28 15 mm) 2 4 6
motorola mpc7410 risc microprocessor hardware specifications 45 document revision history 1.9 document revision history table 16 provides a revision history for this hardware specification. table 16. document revision history rev. no. substantive change(s) 0 initial release. 0.1 minor updates. 0.2 corrected section 1.3?technology from 0.13 m to 0.18 m . updated table 7?adds power consumption numbers; adds note on estimated decrease w/o altivec. updated table 8?adds minimun values for processor frequency and vco frequency. updated table 9?input setup, output valid times, output hold times, sysclk to output high impedance. updated table 11?l2sync_in to high impedance. updated figure 17?mechanical dimensions, adds capacitor pad dimensions. 0.3 added 3.3 v support on the processor bus (bvsel). table 7?update typical and maximum power numbers for full-on mode in. removed note 4. reworded notes 2 and 3. table 9, note 2?removed reference to application note. figure 17?corrected side view datum a to be datum c. section 1.8.7?added ci and wt to transfer attribute signals requiring pull-ups. section 1.8.7?added 1-k ? pull-up recommendation to gbl when gbl is not connected. table 2? added pull-down resistance necessary for internally pulled-up voltage select pins. added 3.3-v support for bvsel. table 13?added note 14 for bvsel, l2vsel, and trst pins to address pull-down resistance necessary for these internally pulled-up pins to recognize a low signal. table 6?lowered 2.5 v cv ih from 2.2 to 2.0 v to be compatible with v oh of the mpc107. added support for 3.3-v processor bus. table 15?modified note 1, use l2cr[l2sl] for l2clk frequency less than 150 mhz. table 8?revised note 2 discussing for 3.3-v bus voltage support. table 14?added note 5, do not use pl off during power-up sequence. table 1?update output hold times (t l2chox ). 1.0 section 1.3 and table 3?revised ov dd from 3.3 v 100 mv to 3.3 v 165 mv. table 13?removed unsupported pll configurations. table 12?added note 15 for minimum mcp pulse width, correct note 3 for 3.3-v processor bus support. table 13?revised note 3 to include emulator tool development. table 14?removed unsupported core-to-l2 example frequencies. section 1.8.8?updated heat sink vendors list. section 1.8.8.2?updated interface vendors list.
46 mpc7410 risc microprocessor hardware specifications motorola document revision history document revision history table 1?updated voltage sequencing requirements notes 3 and 4. table 4?updated/added thermal characteristics. table 5?removed table and tau related information, tau is no longer supported. table 6?updated i in and i tsi leakage current specs. section 1.8.3?removed section. section 1.10?reformatted section. section 1.8.6?changed recommended pull-up resistor value to 1 kw?5 kw. added aack , tea , and ts to control signals needing pull-ups. added pull-up resistor value recomendation for l1_tstclk, l2_tstclk, and lssd_mode factory test signals. section 1.8.7?revised text regarding connection of trst . combined figure 22, figure 23, and table 17, into figure 21. table 7?corrected min vco frequencies from 450 to 700 mhz to match min processor frequency of 350 mhz. table 2?added note 3 to clarify bvsel for revisions prior to rev. e which do not support 3.3 v ov dd . table 3?added notes 5 and 6 to clarify bvsel for revisions prior to rev. e which do not support 3.3 v ov dd . table 5?added note 8 regarding dc voltage limits for jtag signals. 1.1 internal release. table 12?added note 16 for abb /amon and dbb /dmon signal clarification. table 12?changed chk note 4 reference to note 2, signal is for factory test only. changed previous note 4 (chk related) to now provide additional pll info. table 1?modified maximum value for ov dd from ?0.3 to 3.465 to now be ?0.3 to 3.6 and l2ov dd from ?0.3 to 2.6 to now be ?0.3 to 2.8. modified note 6, ov dd for revisions prior to rev. 1.4 have maximum value for ov dd of ?0.3 to 2.8. table 8?removed note 12. l2_tstclk is for factory use only (see table 12, note 2). section 1.10.2?revised section to include nomenclature tables for part markings not covered by this spec. figure 2?added that under/overshoot for l2ov dd references t l2clk while ov dd references t sysclk . table 4?added hcte package (hx package descriptor) thermal characteristics. section 1.5?added hcte package (hx package descriptor). both the cbga and hcte packages have the same pin assignments. section 1.6?added hcte package (hx package descriptor). both the cbga and hcte packages have the same pinout listings. section 1.7?added hcte package (hx package descriptor). both the cbga and hcte packages have the same package parameters and dimensions. table 17?added hcte package (hx package descriptor) to part numbering nomenclature. table 21?added mpc7410thxnnnle extended temperature hcte package part numbers and part number specification document reference. table 16. document revision history (continued) rev. no. substantive change(s)
motorola mpc7410 risc microprocessor hardware specifications 47 document revision history 2 public release, includes rev 1.1 changes. section 1.7.2?added package capacitor values. section 1.8.6?added recommendation that strong pull-up/down resistors be used on the pll_cfg[0:3] signals. table 8?removed mode input setup and hold times. these inputs adhere to the general input setup and hold specifications. figure 5?revised mode input diagram to show sample points around hreset negation. section 1.3?added hcte package description. figure 22?added note 6 to emphasize that cop emulator and target board need to be able to drive hreset and trst independently to the cpu. section 1.8.2?revised section for hcte package. added text and figure for av dd filter for the cbga package. section 1.8.6?removed aack , tea , and ts from control signals requiring pull-ups. removed tbst from snooped transfer attribute list. tbst is an output and is not snooped. 3 table 6?changed note 1 to specify that ov dd and l2ov dd power is typically <5% of v dd power. figure 17?revised diagram and dimensions to specify ?cap regions? versus individual cap measurements. moved individual capacitor placement to separate figure. figure 18?added this figure to show each individual capacitor placement and value. figure 22?updated cop connector diagram to recommend a weak pull-up resistor on tck. table 16. document revision history (continued) rev. no. substantive change(s)
48 mpc7410 risc microprocessor hardware specifications motorola ordering information ordering information 1.10 ordering information ordering information for the parts fully covered by this specification document is provided in section 1.10.1, ?part numbers addressed by this specification.? section 1.10.2, ?part numbers not fully addressed by this document,? lists the part numbers which do not fully conform to the specifications of this document. these special part numbers require an additional document called a part number specification. 1.10.1 part numbers addressed by this specification table 17 provides the motorola part numbering nomenclature for the mpc7410 note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. each part number also contains a revision code which refers to the die mask revision number. table 17. part numbering nomenclature mpc 7410 xx nnn x x product code part identifier package 1 processor frequency 2 application modifier revision level mpc 7410 rx = cbga 400 450 500 l: 1.8 v 100 mv 0 to 105 c c: 1.2; pvr = 800c 1102 d: 1.3; pvr = 800c 1103 e: 1.4; pvr = 800c 1104 hx = hcte e: 1.4; pvr = 800c 1104 notes: 1. see section 1.7, ?package description,? for more information on available package types and table 4 for more information on thermal characteristics. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies.
motorola mpc7410 risc microprocessor hardware specifications 49 ordering information 1.10.2 part numbers not fully addressed by this document parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document, as described in the following tables. table 18. part numbers address by mpc7410rxnnnpx series part number specifications mpc 7410 rx nnn p x product code part identifier package processor frequency 1 application modifier revision level mpc 7410 rx = cbga 450 500 550 p: 2.0 v 50 mv 0 to 65 c c: 1.2; pvr = 800c 1102 1 d: 1.3; pvr = 800c 1103 2 e: 1.4; pvr = 800c 1104 3 notes: document order numbers: 1. mpc7410pcpns. 2. mpc7410pdpns. 3. mpc7410pepns. table 19. part numbers address by mp c7410rxnnnne part numb er specification mpc 7410 rx nnn ne product code part identifier package processor frequency 1 application modifier revision level mpc 7410 rx = cbga 400 450 500 n: 1.5 v 50 mv e: 1.4; pvr = 800c 1104 note: document order number: mpc7410nepns. table 20. part numbers address by mpc7410trxnnnne part number specification mpc 7410 t rx nnn ne product code part identifier process descriptor package processor frequency 1 application modifier revision level mpc 7410 t: ?40 to 105 c rx = cbga 400 450 n: 1.5 v 50 mv e: 1.4; pvr = 800c 1104 note: document order number: mpc7410trxnepns.
50 mpc7410 risc microprocessor hardware specifications motorola ordering information ordering information 1.10.3 part marking parts are marked as the example shown in figure 28. figure 28. part marking for bga device table 21. part numbers address by mpc7410trxnnnle and mpc7410thxnnnle part number specifications mpc 7410 t xx nnn le product code part identifier process descriptor package processor frequency 1 application modifier revision level mpc 7410 t: ?40 to 105 crx=cbga 1 hx = hcte 2 400 450 500 l: 1.8 v 100 mv e: 1.4; pvr = 800c 1104 notes: document order numbers: 1. mpc7410trxlepns. 2. mpc7410thxlepns. cbga mpc7410 rxnnnle mmmmmm awlyywwa 7410 notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states . mmmmmm is the 6-digit mask number. awlyywwa is the traceability code.
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mpc7410ec how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-480-768-2130 (800) 521-6274 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: (800) 521-6274 home page: www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. the described product is a powerpc microprocessor. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their resp ective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003

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